1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to the structure of a compensation capacitor in DRAM.
2. Description of the Related Art
Conventionally, a semiconductor device, which is typically DRAM (Dynamic Random Access Memory), is provided with an internal power supply. The internal power supply supplies power to circuitry which is mounted on a substrate and which performs predetermined functions. Although the internal power supply supplies power to the circuitry when the circuitry is in operation, a large variation in voltage may occur and the operation of the semiconductor device is apt to become instable, if the power is supplied only by the internal power supply. For this reason, so-called compensation capacitor is generally provided on a substrate and is connected to the internal power to stabilize the voltage.
The structure of a prior art compensation capacitor will be described with reference to drawings. FIGS. 1A and 1B are a top plan view and a cross-sectional view illustrating the basic structure of a unit cell of a compensation capacitor, respectively. FIG. 2 is a top plan view of a compensation capacitor which has many unit cells that are arranged in array. Diffusion layer 102, dielectric layer 103, and gate electrode 104 are stacked in this order on a substrate, not shown. Diffusion layer 102 and gate electrode 104 are formed in a plurality of rows. Each row of diffusion layer 102 and each row of gate electrode 104 extend in a perpendicular relationship to one another, as shown in FIG. 2. An intersection of diffusion layer 102 and gate electrode 104 defines overlap portion 111 in which diffusion layer 102, dielectric layer 103 and gate electrode 104 overlap with each other to form a capacitor. Forming diffusion layer 102 and gate electrode 104 in such a plurality of individual rows facilitates the formation of many overlap portions 111, in which diffusion layer 102 and gate electrode 104 overlap with each other, leading to efficient formation of capacitors. Contacts 107 extend from diffusion layer 102 to metal layer 106 in the direction of stacking, with the end thereof in contact with metal layer 106. Insulating layer 105 is disposed between dielectric layer 103 and metal layer 106. Metal layer 106 further extends in parallel with the stacked layers, and is grounded. The rows of gate electrode 104 extend in parallel with the stacked layers, and are connected to power supply VDD row by row through contacts 109. Thus each row is applied with a predetermined voltage. Since the interface with power supply VDD is provided on one side of compensation capacitor 134, contacts 109 are arranged in a line, as illustrated in FIG. 2.
In general, since the main portion of DRAM is formed in the form of a MOS (Metal Oxide Semiconductor) transistor, a compensation capacitor has a similar configuration. A silicon oxide film, which forms a gate insulating film as a part of the gate in a memory unit, not shown, can also be utilized as dielectric layer 103 of compensation capacitor 134. Consequently, dielectric layer 103 of compensation capacitor 134, which is made of a silicon oxide film, can be formed together with the memory cell at one time to simplify the manufacturing process.
As described above, since the compensation capacitor is generally formed in multiple layers due to the configuration which is similar to that of main portions it is important to make each layer flat. A flat surface can be obtained by prior art planarization techniques, and among others, the chemical mechanical polishing method (CMP method) is often used as a planarization technique for semiconductor devices. The CMP method uses both the chemical polishing effect and the mechanical polishing effect of an abrasive in order to planarize a surface. However, when a surface that is to be polished includes an area that is covered with an insulating material, and the remaining area includes metal wires or contacts, a sufficiently flat surface cannot be obtained by the CMP method in many cases, if the insulating material is irregularly distributed. Specifically, the area that is widely covered with an insulating material is excessively polished as compared with the remaining area, and the resultant deep recesses may cause defects such as erosion and dishing. For this reason, dummy patterns may be provided on an area that is covered with an insulating material in order to obtain a flat surface in the CMP process, as disclosed in Japanese Patent Laid-open Publication No. 2001-274255 and 2002-9161.
However, since dummy patterns, which are effective in achieving a flat surface, are provided only for the purposes of planarization, they are of no use after the semiconductor device has been finished. The dummy patterns which are provided for such a purpose are not fabricated with sufficient tolerance that would allow them to be used for other purposes.
Further, there are the following disadvantages other than the foregoing in prior art. Specifically, in order to reduce wire lengths and to limit influence on the performance, it is desirable that the compensation capacitor is arranged in the vicinity of an internal power supply because of its close association with the internal power supply. However, actually, the compensation capacitor is not necessarily arranged at ideal locations for reason such as interference with other circuit elements, and in many cases, is arranged in unused areas after the arrangement of other circuit elements are determined. As a result, if there are obstacles such as other circuit elements that are near the compensation capacitor, then the compensation capacitor must be arranged in an irregular shape in order to avoid interference with the obstacles. FIG. 3 is a top plan view of a compensation capacitor that is arranged in the vicinity of obstacles. In order to detour around obstacles 111a-111c, gate electrode 104 cannot linearly extend toward a location which connects with power supply VDD. Accordingly, additional connections 104x, 104y must be provided in order to connect gate electrodes which are not connected to power supply VDD to gate electrodes which are connected to power supply VDD. Since the arrangement of detour routes cannot be standardized because of the dependency on the arrangement of obstacles 111a-111c, wiring operations must be performed on a case-by-case basis after the compensation capacitor is arranged, leading to worsened operational efficiency. In addition, even if a compensation capacitor could be arranged at a location which would not cause such a disadvantage, dummy patterns would have to be formed in the vacant area in order to avoid the aforementioned problem in the CMP process. Thus, operational efficiency will be worsened in either case.